China is gut punching Moore’s Law and the roughly one-year cadence for major chip releases adopted by the Intel, AMD, Nvidia and others.
The government-backed Chinese Academy of Sciences, which is developing open-source RISC-V performance processor, says it will release major design upgrades every six months. CAS is hoping that the accelerated release of chip designs will build up momentum and support for its open-source project.
RISC-V is based on an open-source instruction architecture, and is royalty free, meaning companies can adopt designs without paying licensing fees.
CAS’ first XiangShan chip, called Yanqihu, was taped out in July 2021. Its successor, called Nanhu, was announced on Monday with major performance and architectural upgrades, and will be out early in 2022.
“For us, we want to launch a startup to commercialize, but we hope there are some other companies to do that,” said Yungang Bao, professor at Chinese Academy of Sciences’ Institute of Computing Technology, during a presentation at the RISC-V Summit in San Francisco.
“We would like to see a company like Red Hat for RISC-V,” Yungang said.
China has made the development of homegrown chips a national priority to catch up with the US. China’s also backing chips made with designs from ARM, which charges licensing fees for its intellectual property. Alibaba has deployed RISC-V server chips in its cloud service and open-sourced some designs.
The six-month release cycle is tied to the increased pace of new features being ratified by RISC-V Foundation, which created the ISA.
“One of the things that’s really important to realize is in 2020 we ratified zero specs. In 2021 we did 16, including some huge things like vector,” Mark Himelstein, chief technology officer of RISC-V International, told The Register in an interview on Monday.
The first XiangShan chip, called Yanqihu, was compared to SiFive’s P550, and viewed as a mainstream computing competitor to ARM’s Cortex-A76 core. Yanqihu was made optimized for the 28-nm process.
The new XiangShan chip, called Nanhu, is designed for the 14-nm process, ostensibly to be made by SMIC. It is based on the 64-bit RV64GCBK design, with the BK identifying support for new extensions.
Given the cooperative nature of RISC-V, some of Nanhu’s new features draw from SiFive designs like the Block Inclusive Cache.
In a slide deck the Nanhu chip was benchmarked on SPEC2006 as being anywhere up to twice faster than its predecessor. The new dual-core chip design operates at a frequency of 2.0GHz, compared to the predecessor chip, which was single-core at 1.3GHz.
The design has a revised front-end and back-end designs to increase throughput and performance. The goal was “to achieve a higher branch prediction accuracy and higher fetch throughput,” Yungang said in the presentation.
The new architecture optimizes the execution unit with support for more instructions, including bit manipulation and scalar crypto extensions.
“Now it also supports instruction fusion for common cases,” Yungang said.
It also has a IEEE754-compliant floating point unit called Fudian.
For the load store unit, there is support for new features that include customized and configurable physical memory attributes, physical memory protection, and ECC for all three levels – L1, L2, L3 – of cache. Yungang said there was a 30 per cent increase in IPC (instructions per cycle) in memory sensitive benchmarks. ®