Tech

Intel bets on packaging to keep Moore’s Law on life support

While some have given up on Moore’s Law, Intel CEO Pat Gelsinger clearly hasn’t. “For decades now, I’ve been in the debate: is Moore’s Law dead? And the answer is no,” he said, during his keynote at the Intel Innovation event this week.

Despite an ample number of naysayers, Gelsinger argues there is plenty of untapped life in the law when it comes to transistor design, power delivery, lithography, and packaging for 100-billion-transistor dies in the near future, and trillions of transistors in a single package by the end of the decade.

At the core of the life-extension belief is advanced packaging. According to Gelsinger, and anyone else paying attention to chip fabrication, we’re approaching the limits of what can be practically achieved on a single die. “Even Gordon Moore, when he wrote his original paper on Moore’s law, saw this day of reckoning where we’ll need to build larger systems out of smaller functions, combining heterogeneous and customized solutions,” said the chief exec.

Intel is betting on its packaging technology and heterogeneous dies – placing different types of dies in a single processor package, all connected up internally – to keep Moore’s law alive a little bit longer. You tend to get better manufacturing yields when making lots of smaller dies, versus big monolithic ones, among other benefits.

This is just what, for one, AMD has been doing for years successfully, and arguably helped fuel its rejuvenation as a supplier of x86 chips. AMD has been packing multiple dies of Zen CPU cores and IO circuitry into individual processor packages, selling them as its Ryzen PC and Epyc server chips – the dies, aka chiplets, being made mostly by TSMC and some by GlobalFoundries, depending on the model.

Not to mention Nvidia and Apple are also moving to multi-die packages, each in their own way.

Intel’s following suit. Its EMIB and Foveros 2D and 3D multi-die packaging tech will be at the heart of its Sapphire Rapids server CPUs and Ponte Vecchio accelerator GPUs, though neither of them are commercially available quite yet.

Intel’s ambitions for this packaging tech aren’t limited to its own silicon. The company is a founding member of the Universal Chiplet Interconnect Express (UCIe) consortium working to standardize the way chiplets from various vendors talk to one another. UCIe has already seen buy-in from some of the largest chipmakers and foundry operators, including TSMC and Samsung Electronics.

Gelsinger painted a picture in which Intel Foundry Services (IFS) — the company’s contract chip manufacturing arm — would package chiplets from Intel, TSMC, GlobalFoundries, Texas Instruments, and others into single cohesive products.

Intel is already doing this to some degree with its Ponte Vecchio platform, which uses its EMIB and Foveros tech to package TSMC-manufactured dies for its upcoming datacenter-class GPUs. And next year’s Meteor Lake CPUs are expected to use a combination of TSMC and Intel dies for the GPU and CPU respectively.

Further, Gelsinger sees such packing tech as one of the company’s more attractive foundry services. “IFS will usher in what we call the systems foundry era,” where the focus shifts from system-on-chip to system-in-a-package, he said.

Speaking to the press after the keynote, Gelsinger said Intel was committed to an open chiplet ecosystem. This means if someone wants to use Intel chiplets with another foundry’s packaging tech, the chipmaker will support that use case. Companies like LightMatter, Tesla, Cerebras, and others are already using advantaged packaging techniques like TSMC’s chip-on-wafer-on-substrate tech to stitch together multiple dies. So, Intel has no shortage of competition in this arena.

Intel’s process problem

Of course, much of this strategy is contingent on Intel staying competitive when it comes to process tech. “You’ve got to be a great wafer foundry. We’re not debating that,” Gelsinger said, in what appears to be an allusion to the chipmaker’s difficulty bringing its 7nm “Intel 4” process node to market.

In Q2 2020, amid a global pandemic, supply-chain shortages, and lockdowns, an otherwise solid quarter for Intel was soured by news that flaws had been discovered in the chipmaker’s 7nm process, delaying its development by roughly a year.

During the keynote this week, however, it was Intel’s upcoming 18a process that Gelsinger was talking up. This is in part because Intel plans to move past 7nm in a relatively short order. Assuming Intel can keep to its February roadmap, its Meteor Lake client processors should be among the first to use the long-delayed process tech. But, for its 15th-gen chips, codenamed Arrow Lake, Intel plans to switch to its 20a process, which uses a gate-all-around transistor design. The “a” in 20a stands for ångströms, and at 10 ångströms to a nanometer, that translates to 2nm. 18a will be a refinement on that node.

IBM, which Intel engaged to develop “next–generation logic and packaging technologies” shortly after Gelsinger took over as CEO, demoed a 2nm process node developed in collaboration with Samsung early last year. Whether the two are related is unclear, but development on Intel’s next-gen process tech is going well, according to Gelsinger. He claims the process design kit for 18a is already in the hands of chip designers, and the chipmaker expects to tape out the first test chips based on the node before the end of the year. ®


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